The present invention relates to a gas discharge display apparatus consisting of a gas discharge display panel for displaying characters, graphics etc. by means of light emitted by electrical discharge in a gaseous plasma, and a drive circuit for driving the display panel.
FIG. 1 shows an oblique partial expanded view of a typical prior art example of a gas discharge display panel, while FIG. 2 shows a partial cross-sectional view of the display panel of FIG. 1. A plurality of anodes 2a, 2b, . . . each formed as a thin stripe are successively arrayed at regular spacings along the vertical direction (which will be referred to in the following as the Y-direction) upon the inner surface of a plate member formed of an optically transparent material, i.e. a glass faceplate 1. A dielectric layer 3, a common electrode 4 which is coupled to a fixed potential, and an insulating layer 5 are sequentially formed over the anodes 2a, 2b, . . . , in that order, to thereby constitute a plurality of capacitors which are coupled between respective ones of the anodes 2a, 2b, . . . and the fixed potential. A plurality of cathodes 7a, 7b, . . . , each formed as a thin stripe, are formed upon the inner face of a rear glass plate 6, aligned at regular spacings along the horizontal direction (referred to in the following as the X-direction), i.e. at right angles to the anodes. A plurality of dielectric partitioning members 8a, 8b, . . . are arrayed along the Y-direction.
As shown in FIG. 2, the glass faceplate 1 and the rear glass plate 6 are mutually bonded to form an enclosed hermetically sealed chamber therebetween, by means of a layer 9 of a glass having a low melting point, which is formed around the peripheries of plates 1 and 6. A mixture of neon and argon gases together with a small quantity of mercury vapor is introduced at low pressure into the interior of the sealed chamber formed between plates 1 and 6. A gas discharge display panel having such a configuration is disclosed in various prior art references such as in Japanese patent provisional publication No. 54-151326.
With a gas discharge display panel having the configuration described above, a plurality of regions of mutual intersection are formed between the anodes 2a, 2b, . . . and the cathodes 7a, 7b, . . . Each of these regions constitutes a display element, i.e. a dot element which can be selectively set to a light-emissive or a non-emissive state. The light-emissive state of a dot element is established by applying a potential between the corresponding anode and cathode of sufficient amplitude to produce a relatively high level of current flow through the gas within the display panel, at that region of intersection, i.e. to produce a plasma discharge. The non-emissive state of a dot results when the amplitude of the potential applied between the corresponding anode and cathode is made sufficiently low that only a very low level of current flow occurs between the corresponding anode and cathode, whereby a substantially negligible level of light emission is produced from that dot element. This substantially non-emissive status will be referred to in the following as the slight discharge state, while the aforementioned light-emissive status will be referred to as the displaying discharge state.
The basic principles of operation of the gas discharge display panel described above will be described referring to the circuit diagram of FIG. 3, which shows the general configuration of a drive circuit for driving the display panel of FIGS. 1 and 2. In FIG. 3, one anode 2a of the display panel of FIG. 1 is shown, together with five of the cathodes 7a. 7b, . . . 7e, and typical drive circuit components connected thereto. Scanning along the Y-direction is performed by sequentially setting to the ON state (in the following, the closed state of a switch or the conducting state of a switching transistor will be referred to as the ON state, and the open state of a switch or the non-conducting state of a switching transistor as the OFF state) each of the cathode switches 1Oa, 1Ob, . . . 1Oe, with each switch being left in the ON state during a fixed time interval referred to in the following as a cathode scanning interval. In this embodiment, each cathode is connected to ground potential during the corresponding cathode scanning interval, and is connected to a +100 V potential at all other times. The potential to which each cathode is connected during the corresponding cathode scanning interval will be referred to in the following as the cathode selection potential.
During such a cathode scanning interval, if for example anode switch 11a is set to the ON state, then a potential equal to the difference between the anode activation potential and the cathode selection potential will be applied between anode 2a and the cathode which is currently selected. This potential difference is determined such that a high level of current flow will occur in the region of intersection of anode 2a and the selected cathode, i.e. the display discharge state will be established for the corresponding display element. If on the other hand anode switch 11a is held in the open state, i.e. the OFF state during a cathode scanning interval, then (as described in detail hereinafter) only a very low amount of current will momentarily flow through the corresponding intersection region, i.e. the corresponding display element is held in the non-emissive discharge state.
The operation of the circuit of FIG. 3 is illustrated in the waveform diagram of FIG. 4, in which it is assumed that the display elements at the intersections of cathodes 7a and 7c and anode 2a are set in the displaying discharge state, while the display elements at the intersections of cathodes 7b, 7d and 7e are set in the slight discharge state. FIG. 4(a) shows the corresponding ON/OFF switching sequence of anode switch 11a, while the corresponding waveforms of the potential Va of the anode 2a, and the discharge current Ia which flows through anode 2a, are respectively shown in FIGS. 4(b) and 4(c). The corresponding variations in potential of cathodes 7a, 7b, . . . , 7e are shown in FIGS. 4(d), 4(e), . . . , 4(h) respectively. As shown, a blanking interval of duration t.sub.0 is provided between each pair of successive cathode scanning intervals. Each cathode scanning interval is of duration t.sub.1. One reason for providing these blanking intervals is that transistors are used to perform the functions of cathode switches 1Oa, 1Ob, . . . , 1Oe, and switching delays will be introduced by these transistors. In order to prevent errors in operation being caused by these delay times, immediately after a cathode has been addressed during a cathode selection interval t.sub.1, a slight discharge current flow is momentarily produced between that cathode and each anode corresponding to a display element which has not been set in the light-emitting state. This current flow is produced as follows. Due to the capacitance of anode 2a for example, indicated by reference numeral 12 in FIG. 3 (assumed to have a value Cs), and the capacitance Ca of a capacitor 4a which is provided internally within the gas discharge display panel 1 and coupled to anode 2a, the potential Va of the anode 2a approaches a value Vs (determined by a power source 13) during each of the blanking intervals t.sub.0. If the succeeding t.sub.1 interval is an anode ON potential interval, i.e. an interval in which the anode switch 11a is held in the ON state, the anode potential Va will then fall to a discharge maintaining potential Vm and remain at that potential during that anode ON t.sub.1 interval. A relatively high-amplitude discharge current Ia thereby flows through anode series resistor 14 (having resistance value Ra), with the value of this current Ia being equal to (Vs-Vm)/Ra.
If on the other hand the anode switch 11a is held in the OFF state during a t.sub.1 interval following a t.sub.0 interval, then the charge which has accumulated on the stray capacitance 12 of anode 2a and on capacitor 4a will be discharged during that t.sub.1 interval, as a discharge current which flows through the region of intersection of anode 2a and the corresponding cathode. The magnitude of the stored charge Q which is thereby discharged is given as: EQU Q=(Cs+Ca)x(Vs-Vd)
where Vd is the anode potential upon completion of the discharging the stored charge. The resultant discharge through the gas between anode 2a and the corresponding cathode will be referred to as a slight discharge, in the following. This slight discharge is terminated after a short time has elapsed. As a result of such a slight discharge being periodically produced in each electrode intersection region at which the displaying discharge state is not produced, charged particles and excitation atoms become diffused within the adjacent intersection region (positioned above an immediately adjacent cathode to that which is currently selected) which will be addressed during the succeeding cathode scanning interval. This serves to improve the reliability of establishing the displaying discharge state, and to ensure a more rapid build-up of discharge current flow between anode and cathode to initiate that state, thereby ensuring more stable operation.
FIG. 5 is a block circuit diagram of a practical example of a prior art gas discharge display apparatus formed of a gas discharge display panel and drive circuit such as described above. A plurality of transistors 15a, 15b, . . . 15e which perform the functions of the cathode switches 1Oa, 1Ob, . . . 10e described above, are respectively connected to a scanning circuit 16. A horizontal sync signal (comprising a train of pulses having a period equal to (t.sub.0 +t.sub.1) and a vertical sync signal consisting of a train of pulses whose period determines the refresh rate of the display, are supplied to a scanning signal generating circuit 17. The scanning signal generating circuit 17 thereby supplies a scanning signal to scanning circuit 16, which determines the timings and durations of the blanking intervals t.sub.0 and the cathode ON potential intervals t.sub.1.
Control of anodes 2a, 2b, . . . , i.e. the control of data display, is executed by an anode switch circuit 18. This circuit performs the functions of anode switch 11 shown in FIG. 3, for each of the anodes 2a 2b, . . . , to control the application of discharge voltages to the respective anodes. The anode switch circuit 18 is controlled by output signals produced from a latch circuit 19, with these signals determining the timings at which switches within the anode switch circuit 18 are set to the ON and OFF (i.e. closed and open) states to thereby establish the displaying discharge state and the slight discharge state respectively of the display elements, in accordance with the data to be displayed. Upon completion of each cathode scanning interval, the display data which is to be displayed by the next cathode to be addressed is transferred to the latch circuit 19 from a shift register 20, under the control of a strobe signal which is applied to latch circuit 19 from a data read-in signal generating circuit 21. A charging signal generating circuit 22 applies a charging signal to the anode switch circuit during each of the cathode blanking intervals t.sub.0. This charging signal acts to set each of the anodes 2a, 2b, . . . to the ON state for the duration of each of the cathode blanking intervals, as illustrated in FIG. 4(a). The above circuits, in conjunction with the anode coupling resistors 14 and the capacitors 4a serve to control the display operation. Each of the capacitors 4a has a capacitance value Ca which is approximately 20 picofarads, and serves to produce the slight discharge current flow described above, in conjunction with the stray capacitance 12 of the corresponding anode.
FIG. 6 shows an example of a specific circuit for anode switch circuit 18, while FIG. 7 shows waveforms at various points in the circuit of FIG. 6. In this example the anode switch circuit 18 consists of a set of switch circuits for the respective anodes 2a, 2b, . . . , 2z which are respectively designated as 18a, 18b, . . . ,18z. Each of these switch circuits 18a, 18b, . . . ,18z in this example consists of an OR gate 23 which is coupled to receive a data signal from latch circuit 19 and a charging signal from charging signal generating circuit 22, a FET 24a controlled by the OR gate 23 output, and an output transistor 24b which is controlled by the output from FET 24a. As shown, during each time interval t.sub.1 in which cathode 7c, for example, is being scanned, display data signals representing data to be displayed by the next cathode in the scanning sequence (7d) is are supplied to shift register 20 in response to a series of shift clock pulses which are input to shift register 20. The display data signals are then transferred to the latch circuit 19 upon the rising edge of a strobe signal pulse which is produced from the data readout signal generating circuit 21. During the next cathode blanking interval t.sub.0, a charging signal signal produced from the charging signal generating circuit 22 goes to the H (i.e. high) logic level, and as a result the output from each OR gate 23 in the anode switch circuit 18 is forcibly held at the H level during the t.sub.0 interval. As a result, all of the anode switches are held in the ON state. During that ON state condition, i.e. while the charging signal is at the H level, a potential of 200 V applied from a power source produces a flow of charging current which passes through the output transistor 24b of each anode, into the corresponding anode capacitor 4a and the corresponding stray capacitance 12, thereby charging these capacitors towards +200 V. When the charging signal falls to the L (i.e. low ) level at the end of that t.sub.0 blanking interval, the output transistor 24b in each of switching circuits 18a, 18b, . . . ,18z is set either to the ON or to the OFF state in accordance with the corresponding data output signal from latch circuit 19. The corresponding display elements of the next cathode to be scanned, i.e. cathode 7d, are thereby set to the light-emitting or non-light emitting states in accordance with the display data.
The operation during scanning of each of the other cathodes is identical to that for cathodes 7c and 7d described above.
If a gas discharge display apparatus of the form described above is designed for high-resolution display, then only a small spacing will be provided between adjacent ones of the anodes 2a, 2b, . . . will be spaced very closely together. Thus, the spacings between successive dielectric partitioning members 8a, 8b, . . . will also be very small. As a result, the charged particles and excitation atoms which are generated by the slight discharge process described above, i.e. resulting from discharge of an accumulation of charge upon capacitors and stray capacitances coupled to the respective anodes, will readily recombine and be thereby eliminated. In addition, the diffusion resistance between adjacent electrode intersection regions will tend to be high, so that generation of the slight discharge will not occur in a stable manner, i.e. may occur only intermittently. Furthermore, in the case of a high-resolution gas discharge display panel there will be a relatively large amount of mutual capacitive coupling between the anodes, and this further tends to extinguish the slight discharge described above. Referring to FIG. 5 and assuming for example that the displaying discharge state is established at the intersection region between electrodes 2b and 7d, which will be referred to as the region (2b.multidot.7d) and that the slight discharge state is established in the region (2c.multidot.7d) between anode 2c and cathode 7d, then the charged particles and excitation atoms which should preferably diffuse to the next intersection regions to be scanned, i.e. regions (2b.multidot.7e) and (2c.multidot.7e) will in fact almost entirely diffuse into the intersection region (2b.multidot.7e) rather than into region (2c.multidot.7e). Furthermore since the amount of capacitance C.sub.sa between the anodes is substantial, the slight discharge which should occur in the intersection region (2c.multidot.7e) will tend to flow into the inter-anode capacitance C.sub.sa and hence into the intersection region (2b.multidot. 7e). As a result, generation of the slight discharge at the intersection region (2c.multidot.7e) may occur only intermittently, or may fail to occur.
It would be possible to overcome the problem described above, i.e. failure or intermittent occurrence of the slight discharge condition, by increasing the value of capacitance of the capacitors 4a which are internally provided within the gas discharge display panel and connected to respective ones of the anodes 2a, 2b, . . . , and by increasing the level of load resistance through which the slight discharge must flow. However if the value of capacitance of the capacitors 4a is increased, then these capacitors will occupy a substantial amount of display area of the gas discharge display panel. Thus, the display utilization efficiency will be lowered, and manufacturing costs will be increased.